The present invention relates to a multi-layer dopant diffusion barrier for use in III-V semiconductor structures.
Optical communications systems employ a variety of optoelectronic devices. Some of these optoelectronic devices incorporate a structure in which an intrinsic (i) semiconductor layer is disposed between a p-type layer and an n-type layer. This structure is commonly referred to as a PIN structure and the devices as PIN devices. The PIN structure has properties which are useful in optoelectronic devices. For example, the intrinsic layer may have a larger index of refraction than the p and n layers. In this way, a waveguide can be formed, with the p and n layers being cladding layers and the intrinsic layer being the guiding layer of the waveguide. Furthermore, energy band discontinuities in the conduction and valence bands in the PIN structure facilitate carrier confinement within the intrinsic layer, which is useful in many devices. In short, the PIN structure is well suited for a variety of light emitting and detecting optoelectronic device applications.
One material that is used often in PIN devices is indium phosphide (InP). In a PIN structure employing InP, the p-type layer is often fabricated by introducing zinc as a dopant. Although a suitable dopant for forming the p-type layer, zinc can readily diffuse out of the p-type layer due to the higher temperature achieved during the growth of InP.
In addition, many optoelectronic devices are based on a structure commonly known as a buried mesa structure. Often a PIN structure is part of the mesa, and the mesa is disposed between current blocking layers. The current blocking layers provide transverse optical and carrier confinement. In many structures, one or more of the current blocking layers is semi-insulating, iron doped indium phosphide (InP(Fe)). Unfortunately, inter-diffusion of p-dopants from the p-type layer and iron from the semi-insulating InP(Fe) layer may occur. This inter-diffusion may have detrimental effects on device characteristics. The diffusion of the p-type dopants from the p-type layer can result in leakage current in the device; and the diffusion of the iron dopants into the p-type layer can make the p-type layer more resistive. Accordingly, it is desirable to have a barrier layer to prevent the inter-diffusion.
In some conventional structures, an n-InP layer can be used as a dopant barrier layer. The n-InP layer may be disposed between the mesa and the current blocking layers in a buried mesa structure. This is shown in FIG. 5. An n-InP dopant barrier layer 501 is disposed between the mesa 502 and InP(Fe) current blocking layers 503. However, the dopant concentration in the n-InP barrier layer 501 may be relatively high (on the order of about 1018-1019 atoms/cm3) to prevent diffusion of p-type dopants out of the p-type layer 504. Additionally, to ensure appropriate blocking of the dopants, it may be necessary to make the n-InP layer 501 relatively thick, on the order of tens of nanometers. Accordingly, a parasitic pn junction may be formed between the p-type layer 504 and n-type dopant barrier layer 501. This can cause an undesired current leakage path. Moreover, the disposition of the n-type dopant barrier layer 501 between the p-type cladding layer 504 and the current blocking layers 503 can result in an undesired parasitic capacitance component. Parasitic capacitance may be particularly problematic in devices such as electro-absorptive modulators, lasers and digital devices, in general, as it adversely impacts device speed.
Accordingly, what is needed is a dopant diffusion barrier, which effectively blocks diffusion of dopants, while not introducing parasitic elements, such as pn junctions and capacitance, to the device.
The present invention relates to a multi-layer dopant barrier and its method of fabrication for use in semiconductor structures. In an illustrative embodiment, the multi-layer dopant barrier is disposed between a first doped layer and a second doped layer. The multi-layer dopant barrier further includes a first dopant blocking layer adjacent the first doped layer and a second dopant blocking layer adjacent the second doped layer.
In another illustrative embodiment, a technique for fabricating the multi-layer dopant barrier is disclosed. A first dopant blocking layer is formed at a first temperature, and a second dopant blocking layer is formed at a second temperature over the first barrier layer.
In the illustrative embodiments of the present invention, dopant diffusion is significantly reduced. Moreover, parasitic pn junctions and parasitic capacitance of the above discussed prior art are substantially avoided.